IC 74LS90 or 74LS74
Each of these monolithic counters contains four master-slave
flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ’LS90
and divide-by-eight for the ’LS93. All of these counters have a gated zero
reset and the LS90 also has gated set- to-nine inputs for use in BCD nine’s
complement applications.
To use their maximum count length (decade or four bit binary), the B input
is connected to the QA output. The input count pulses are applied to input A and
the outputs are as described in the appropriate truth table. A symmetrical
divide-by-ten count can be obtained from the ’LS90 counters by connecting the QD
output to the A input and applying the input count to the B input which gives a
divide-by-ten square wave at output QA.
74LS90 or 74LS74 table
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight (LS93) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW
clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q0 output of
each device is designed and specified to drive the rated fan-out plus the CP1 input of the device.
A
gated AND asynchronous Master Reset (MR1 • MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes.
BCD Decade (8421) Counter — The CP1 input must be externally connected to the Q0 output. The CP0 input receives the incoming count and a BCD count sequence is produced.
Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. The input count is then applied to the CP1 input and a divide-byten square wave is obtained at output Q0.